Microcontroller

Aka. MCU. A compact integrated circuit designed to control embedded systems.

Includes:

• CPU
• Memory
• I/O interfaces
• Timers and peripherals

Often implemented as a System-on-Chip (SoC)

Microcontrollers are widely used in IoT devices because they:

• consume very little power
• require few external components
• provide built-in I/O capabilities.

Microcontroller Architecture

Hardware Model

Describes the physical structure and electrical characteristics of the microcontroller. Relevant to circuit designers and PCB engineers.

Covers:

• Power supply requirements
  Operating voltage range, current draw, decoupling capacitor placement.
• Clock system
  External crystal or internal RC oscillator frequency; clock distribution to peripherals.
• Bus architecture
  Width and timing of address, data, and control buses between CPU, memory, and peripherals.
• Memory types
  Physical flash, SRAM, and EEPROM cells and their access characteristics.
• Bus timing
  Setup/hold times, read/write cycle lengths; critical for interfacing external memory or peripherals.
• Pin configuration
  Physical pinout, alternate pin functions, drive strength, and logic voltage levels (e.g. 3.3 V vs 5 V).

Programmer’s Model

Represents the microcontroller from the software developer’s perspective. Abstracts away physical implementation details.

Covers:

• Instruction set architecture
  The set of opcodes the CPU can execute; determines what the compiler targets.
• Memory organization
  How the address space is laid out: program memory, data memory, and memory-mapped peripheral registers.
• Register model
  General-purpose registers and special function registers (SFRs) accessible by software.
• ALU capabilities
  Supported arithmetic and logical operations; whether hardware multiply/divide is available.
• Interrupt handling
  Interrupt vector table, priority levels, and enable/flag registers.
• Peripheral device access
  Reading and writing peripheral registers (GPIO, timers, UART, SPI, I²C) via memory-mapped I/O addresses.
• Resource management
  Stack pointer, program counter, status flags, and watchdog control.

I/O Access Methods

Two approaches exist for how software addresses peripheral registers.

Memory-Mapped I/O

Peripheral registers occupy addresses in the same address space as RAM and ROM. The CPU uses ordinary load and store instructions to read and write them. No special I/O instructions are needed.

A memory map partitions the address space into regions:

• Program flash (read-only)
• SRAM (read/write)
• Peripheral registers (read/write, with hardware side effects)
• Boot ROM / configuration fuses

Writing to a peripheral register address does not store a value in RAM — it sends a command to the hardware. Reading from a status register address reads the current hardware state, not a cached value.

Used by: ARM Cortex-M, AVR, PIC, ESP8266/ESP32, and most modern MCUs.

Advantages:

• No separate instruction set needed for I/O
• Peripheral registers accessible with pointer arithmetic in C
• Standard debugging tools (memory inspectors, JTAG) can read peripheral state directly

Volatile Keyword

Compilers may cache memory reads in registers and eliminate repeated loads as an optimisation. Peripheral registers change without CPU involvement, so caching their value produces stale reads.

Declaring a peripheral register pointer as volatile tells the compiler every access must go to the actual address:

volatile uint32_t *GPIOA_ODR = (uint32_t *)0x40020014;

Port-Mapped I/O

Aka. isolated I/O or I/O-mapped I/O. Peripheral registers occupy a separate address space, distinct from memory. Dedicated CPU instructions access them: IN (read from port) and OUT (write to port) on x86.

The address bus carries a separate signal (M/IO̅) to distinguish memory cycles from I/O cycles, so the same numeric address can refer to both a RAM location and a peripheral register without conflict.

Used by: x86 architecture (PC-class processors). Rare in embedded MCUs.

Advantages:

• Peripheral space cannot be accidentally accessed by a stray pointer
• Full memory address space remains available for RAM and ROM

Disadvantages:

• Requires dedicated I/O instructions; C compilers need intrinsics or inline assembly
• Peripherals not visible to standard memory debugging tools

Special Function Registers

On many MCUs (8051, PIC, AVR) peripheral control registers are called Special Function Registers (SFRs). They appear at fixed addresses in the memory map and are named in the device header file so firmware can reference them by name rather than raw address.

DDRB = 0xFF;   // AVR: set all Port B pins as output
PORTB = 0xAA;  // AVR: write pattern to Port B

Components

Microprocessor Unit

Aka. MPU. The central processing unit inside the microcontroller that executes instructions and controls system operations. Uses a specialized or scaled-down processor design. Often based on architectures like 8051, 8048, or 68HC11. Executes instructions and coordinates peripherals.

Memory Subsystems

IoT systems use Howard architecture to improve instruction execution efficiency.

Program Memory

Stores the executable instructions of the microcontroller program. Implemented as flash memory. Read-only during normal program execution.

Flash is non-volatile: contents survive power loss. This makes it suitable for permanent code storage, unlike RAM which loses its contents on power-off.

Why Read-Only During Execution

Flash cells can only be erased in large blocks (pages or sectors), not byte by byte. Erasing forces all bits in the block to 1; writing then selectively drives bits to 0. This erase-before-write cycle takes milliseconds — orders of magnitude slower than instruction execution.

Writing to flash while executing from the same flash block causes a bus conflict: the CPU fetch and the write controller both need the flash bus simultaneously. Most MCUs prevent this in hardware.

For these reasons, flash is only written during:

• Initial programming via ICSP or JTAG
• Firmware update via a bootloader (which copies new code into RAM and executes the write from there)

IP Protection

See Intellectual Property Protection.

Data Memory

Stores variables and temporary program data. Often implemented as RAM. Sometimes structured as a register file for faster access.

Hardware Stack

A dedicated, fixed-depth set of internal registers that stores return addresses for subroutine calls and interrupts. Managed entirely by the CPU in hardware — no software stack pointer maintenance required.

On a software stack (used by ARM, AVR, x86), the stack pointer (SP) register points into a region of RAM. The stack grows into RAM on each call and shrinks on return. On a hardware stack, the return addresses are stored in a separate on-chip register file with no RAM involvement.

Reasons for Use in IoT

• Speed
  Internal register access completes in a single clock cycle. No memory bus cycle is needed, so call and return latency is fixed and minimal.
• Deterministic interrupt response
  Interrupt entry saves the program counter to the hardware stack instantly. No variability from RAM bus arbitration or cache misses.
• RAM conservation
  Constrained 8-bit MCUs (8051: 128 B RAM, PIC: 96–368 B RAM) cannot afford to dedicate a block of their tiny RAM to a call stack. The hardware stack removes this cost entirely.
• No initialisation overhead
  A software stack requires startup code to set the stack pointer before any function call. A hardware stack is ready at reset with no setup.

Limitations

• Fixed depth — PIC has 8 or 31 levels depending on the device; exceeding it silently overwrites the oldest return address
• Deep recursion is impossible
• The programmer must track call depth and ensure nesting never exceeds the limit

Peripheral Modules

Peripheral modules extend the functionality of the microcontroller by enabling interaction with external devices. Each peripheral is controlled by a set of memory-mapped registers: a control register (mode and enable bits), a status register (flags), and one or more data registers.

Categories:

• Timers and counters
• Analog-to-digital converters
• Communication interfaces (UART, SPI, I²C)
• Digital I/O ports

Peripherals act as interfaces between the processor bus and the external environment.

Examples

PIC and AVR support many peripherals. AVR supports analog input/output. Intel 8051 is an older architecture with limited resources which uses 8-bit instruction set. ARM is a newer architecture with more powerful features and better performance, but it is more complex and consumes more power than PIC and AVR.

Startup State

Describes the state of the MCU at the moment execution begins.

Cold Start

MCU powers on from a fully unpowered state.

• All RAM contents are undefined (or zero on some architectures)
• All registers are at hardware reset values
• Oscillators start from rest; both startup delay and oscillator delay apply
• All peripherals must be initialised by software before use
• Longest time-to-operational state

Hot Start

MCU resumes from a low-power sleep mode with RAM and register state retained.

• RAM contents preserved; no re-initialisation required
• Oscillator may still be running or settles faster from a partially-warm state
• Only oscillator delay (if any) applies; startup delay is skipped
• Peripherals that remained powered are already configured
• Fastest time-to-operational state