Analog-to-Digital Conversion

An ADC maps a sampled analog voltage to a binary integer. MCUs process binary values. Sensors output continuously varying voltages.

Here:

• $D$: digital output value
• $V_\text{in}$: input voltage
• $V_\text{ref}$: reference voltage
• $n$: resolution in bits

An $n$-bit ADC produces $2^n$ discrete levels.

Parameters:

• Sampling rate
  Maximum conversions per second.
• Reference voltage
  Upper bound of the measurable input range.

Types

• Parallel
  All bits resolved simultaneously. Fast. Hardware cost scales exponentially with resolution.
• Serial
  Bits resolved 1 at a time over multiple cycles. Lower cost. Slower.

Flash ADC

$2^n - 1$ comparators in parallel, each with a distinct reference from a resistor ladder. All fire simultaneously. A priority encoder converts the thermometer code to binary.

• Fastest: 1 clock cycle per conversion
• Hardware cost grows exponentially with bit depth
• Used in oscilloscopes and high-speed RF sampling

Counter-Ramp ADC

A counter starts at 0 and increments each clock cycle. Its value feeds an internal DAC, producing a staircase voltage. A comparator checks the staircase against $V_{in}$ each cycle. When the staircase exceeds $V_{in}$, the counter is latched as output.

Here:

• $D$: steps to reach $V_{in}$
• $T_{clk}$: clock period

Conversion time varies with $V_{in}$. Full-scale requires up to $2^n - 1$ cycles.

• Simplest serial design: 1 comparator, 1 counter, 1 DAC
• Slower than SAR for most inputs
• Used in low-cost, low-speed applications

Tracking ADC

A counter-ramp variant. Replaces the reset counter with an up/down counter that continuously follows $V_{in}$.

Per clock cycle:

• Counter increments if DAC output is below $V_{in}$
• Counter decrements if DAC output is above $V_{in}$

The counter never resets. Output is always the current counter value.

• No start-conversion trigger needed
• Fast for slowly changing inputs
  Steps $\pm 1$ per cycle to maintain lock.
• Slow for large step changes
  Must slew $\pm 1$ per cycle. Worst case: $2^n$ cycles.
• Unsuitable for multiplexed inputs switching between unrelated voltages

Successive Approximation Register ADC

1 comparator, 1 internal DAC, and an $n$-bit SAR register. Resolves 1 bit per cycle via binary search, MSB to LSB.

Sequence for bit $k$ (starting at $k = n-1$):

1. Set bit $k$ to 1 in the SAR register.
2. Feed the SAR value to the DAC to produce a trial voltage.
3. Compare DAC output to $V_{in}$.
4. If $V_{in} \geq V_{DAC}$: keep bit $k$ at 1. If $V_{in} < V_{DAC}$: clear bit $k$ to 0.
5. Move to bit $k-1$ and repeat.

After $n$ cycles the SAR register holds the final output.

• Exactly $n$ cycles regardless of $V_{in}$
• 1 comparator, 1 DAC, 1 shift register
• Most common in MCUs (ATmega, STM32, ESP32 all use SAR)

Dual-Slope ADC

2-phase operation:

1. Integrate $V_{in}$ for fixed period $T_1$, charging a capacitor.
2. Discharge with fixed $-V_{ref}$. Measure time $T_2$ to reach zero.

Result depends only on the ratio of times, not component tolerances. Noise averages out over $T_1$.

• Very high accuracy and noise rejection
• Slow: conversion takes milliseconds
• Used in digital multimeters and precision instrumentation

Sigma-Delta ADC

Oversamples far above the Nyquist rate, applies noise shaping, then decimation-filters to a high-resolution output.

• Resolution up to 24 bits
• Slow: latency proportional to oversampling ratio
• Used in audio codecs and precision sensors

Comparison

Implementation in MCUs

MCUs expose multiple analog pins but contain only 1 ADC. An analog MUX connects exactly 1 pin to the ADC at a time. The MUX channel is set in software before each conversion.

Analog pins
  A0 ─┐
  A1 ─┤
  A2 ─┼─── MUX ─── Sample & Hold ─── ADC ─── Digital output
  A3 ─┤
  A4 ─┘

A sample-and-hold captures the pin voltage at conversion start and holds it constant for the full duration.

1 ADC is shared across all channels to minimize silicon area. An ADC contains a comparator, an internal DAC, control logic, and reference circuitry. Duplicating it per pin multiplies cost proportionally. A MUX adds only a few transistors per channel.