Communication Interfaces

Interface

Defines the physical layer such as electrical signals, wire count, voltage levels, on-chip hardware peripheral.

2 types:

• Serial
• Parallel

Protocol

Defines the logical layer such as frame structure, addressing, timing rules, error signaling.

These terms are used interchangeably for UART, SPI, and I²C because each standard defines both layers together.

The distinction becomes meaningful when a higher-level protocol runs on top of a physical interface. For example, device-specific register maps carried over the I²C bus are a protocol layered above the I²C physical standard.

Local

Short-range, board-level or chip-to-chip protocols for connecting an MCU to sensors, actuators, and peripherals.

UART

Universal Asynchronous Receiver/Transmitter. Asynchronous: no shared clock. Both ends must be pre-configured to the same baud rate.

Pins: TX (transmit) and RX (receive), crossed between devices.

Frame structure:

[IDLE=HIGH] → [START=LOW] → [D0...D7] → [PARITY?] → [STOP=HIGH]

• Start bit (LOW) signals beginning of transmission.
• 8 data bits follow.
• Optional parity bit for basic error detection.
• Stop bit (HIGH) returns the line to idle.

Properties:

• Full duplex
• Point-to-point only (no bus topology)
• No clock line: receiver samples based on its own internal clock
• Clock drift is tolerated within a single frame but accumulates across many frames
• Common baud rates: 9600, 115200 bps

Used for: serial debug monitor, GPS modules, Bluetooth adapter modules, GSM modems.

SPI

Serial Peripheral Interface. Synchronous: master generates the clock.

Pins:

• SCLK
  Serial clock, driven by master.
• MOSI
  Master out, slave in.
• MISO
  Master in, slave out.
• CS̄
  Chip select, 1 per slave, active LOW.

Transaction sequence:

1. Master asserts CS̄ LOW to select the target slave.
2. Master generates clock pulses on SCLK.
3. On each clock edge, 1 bit is driven on MOSI and 1 bit is sampled from MISO.
4. After $N$ clock cycles, $N$ bits have been exchanged in both directions simultaneously.
5. Master deasserts CS̄ HIGH to end the transaction.

Both master and slave hold a shift register. Each clock edge shifts 1 bit out and 1 bit in at the same time. After 8 edges, a full byte is exchanged in each direction. Sending and receiving cannot be decoupled. Every transmission is simultaneously a reception.

Clock mode is controlled by 2 parameters:

• CPOL
  Clock polarity. Idle state of SCLK. 0 = idle LOW, 1 = idle HIGH.
• CPHA
  Clock phase. Which edge triggers data sampling. 0 = leading edge, 1 = trailing edge.

4 modes result from the combination:

Master and slave must use the same mode. Mode 0 is the most common default.

Properties:

• Full duplex: 1 bit shifted out on MOSI and 1 bit shifted in on MISO per clock edge simultaneously
• Single master, multiple slaves (each slave requires a dedicated CS̄ line)
• No addressing: CS̄ selects the active slave
• No ACK: master cannot detect if a slave is absent or has failed
• Fast: typically 10–100+ MHz
• Pin count scales with slave count: $N$ slaves require $N + 3$ pins total

Used for: displays, SD cards, external ADC/DAC chips, flash memory.

I²C

Inter-Integrated Circuit. Synchronous. 2-wire open-drain bus requiring pull-up resistors on both lines.

Pins: SDA (bidirectional data), SCL (clock).

Any device can pull a line LOW. The pull-up resistor pulls it HIGH when no device is driving it.

Transaction sequence:

1. START condition: SDA goes LOW while SCL is HIGH.
2. Master sends 7-bit device address + 1 R/W bit.
3. Addressed slave responds with ACK (pulls SDA LOW).
4. Data bytes transferred, each followed by ACK from receiver.
5. STOP condition: SDA goes HIGH while SCL is HIGH.

Properties:

• Half duplex
• Multi-master, multi-slave on the same 2 wires
• Up to 127 devices in 7-bit mode, limited by address space and electrical loading
• Each device has a unique 7-bit (or 10-bit) address
• Built-in ACK on every byte
• Standard mode: 100 kHz. Fast mode: 400 kHz. Fast-plus: 1 MHz

Used for: IMUs, temperature and pressure sensors, EEPROMs, real-time clocks.

1-Wire

Single data line (plus ground). Semi-duplex. Supports multiple devices on the same wire, each identified by a unique 64-bit ROM code.

Very low speed. Used where minimal pin count matters: temperature sensors (DS18B20), iButton authentication devices.

Parallel Slave Port

Aka. PSP. A parallel interface that allows an external master processor to read and write the MCU’s internal registers directly over a multi-bit data bus.

Unlike serial interfaces (UART, SPI, I²C), a PSP transfers a word simultaneously across multiple data lines.

Pin groups:

• Data bus
  8 or 16 bidirectional data lines carrying one word per transfer.
• Address lines
  Select which internal register or memory location the master is targeting.
• Control lines
  CS (chip select), RD (read strobe), WR (write strobe). The master asserts these to initiate a transfer.

The external master places an address on the address lines, asserts CS and RD or WR, and the MCU responds by placing data on the bus or latching the incoming word.

Use cases:

• MCU acting as a peripheral co-processor alongside a more powerful host CPU
• Display controllers and memory-mapped peripherals on embedded boards
• High-speed sensor data transfer where serial overhead is too slow

Network

Protocols for connecting IoT devices to local networks or wide-area infrastructure.

Wi-Fi

IEEE 802.11. Operates at 2.4 GHz or 5 GHz. High bandwidth and low latency. High power consumption relative to other wireless IoT protocols.

Used for cloud connectivity, over-the-air updates, and applications requiring high data rates.

Bluetooth and BLE

Operates at 2.4 GHz.

• Bluetooth Classic
  Higher throughput. Used for audio streaming and file transfer.
• Bluetooth Low Energy (BLE)
  Very low power. Short bursts of small data. Used for sensor beacons, wearables, and proximity detection.

Range: approximately 10–100 m depending on environment.

Zigbee

Low-power wireless mesh protocol. Protocol stack, device types, and topologies covered in Non-TCP/IP Wireless Protocols.

Used for: home automation, lighting control, dense sensor networks.

LoRa / LoRaWAN

Operates in sub-GHz ISM bands (868 MHz in Europe, 915 MHz in the Americas). Spread-spectrum modulation enables kilometre-range links at very low transmit power. Very low bandwidth (< 50 kbps).

Used for wide-area sensor deployments: agriculture, smart metering, asset tracking.

Ethernet

IEEE 802.3. Wired. High reliability and deterministic latency. Not affected by wireless interference.

Used in industrial IoT, building automation, and SBC-based devices (Raspberry Pi).

Cellular

NB-IoT and LTE-M are cellular standards designed for IoT:

Low bandwidth, low power, wide area coverage. Devices connect directly to cellular infrastructure without a local gateway.

Used for mobile asset tracking, remote metering, and deployments in areas without Wi-Fi

Comparison