Signal Integrity | Sahithyan's Notes

Pull Resistor

A floating input pin has no external driver. The MCU samples whatever noise or leakage is present, producing unpredictable readings. A pull resistor ties the pin to a known voltage through a high-value resistor (typically $1\ \text{k}\Omega$ – $100\ \text{k}\Omega$ ).

Pull-up Resistor

Connects the pin to $V_{CC}$ . Pin reads HIGH when nothing drives it. A device pulling the line LOW overrides the resistor.

Why Required for MCU Inputs

Floating pins drift HIGH
Input impedance is in the megaohm range. Stray charge from EM fields, adjacent-trace coupling, and RF accumulates on the pin’s parasitic capacitance with no low-impedance path to drain it. CMOS $V_{IH} \approx 0.7 \times V_{CC}$ , so the HIGH region is wide and floating pins tend to land there. Internal ESD leakage paths reinforce the bias toward $V_{CC}$ .
No enforced valid default
MCU input buffers accept any voltage, including the forbidden band. Only the pull resistor enforces a defined idle state.
RC edge degradation
Input-line capacitance and the pull-up form an RC filter. A large resistor rounds edges enough to cause metastability. Keep pull-up values within $1\ \text{k}\Omega$ – $10\ \text{k}\Omega$ .
Safe default on disconnect
If the peripheral loses power or is removed, the pull-up holds the input at a known HIGH.

Pull-down Resistor

Connects the pin to GND. Pin reads LOW when nothing drives it. A device pulling the line HIGH overrides the resistor.

Resistor Value Trade-off

The pull resistor value must satisfy 2 conflicting constraints.

Lower bound

Set by current. For a pull-up with the line driven LOW:

I = \frac{V_{CC}}{R}

Current flows continuously while the line is asserted. Too low a resistance wastes power, stresses the driving transistor, and heats the resistor.

Upper bound

Set by edge speed. The resistor and line capacitance $C_\text{line}$ form an RC circuit:

\tau = R \times C_\text{line}

A high resistance slows rising edges, extending time in the forbidden band. Leakage current also produces a voltage offset:

V_\text{error} = I_\text{leakage} \times R

Typical values:

$1\ \text{k}\Omega$ to $4.7\ \text{k}\Omega$
I²C buses and higher-speed signals.
$4.7\ \text{k}\Omega$ to $10\ \text{k}\Omega$
General-purpose GPIO, buttons, slow signals.

Values above $10\ \text{k}\Omega$ suit only ultra-low-power designs where speed is not a concern. Values below $1\ \text{k}\Omega$ draw excessive current.

Most MCUs include configurable internal pull-ups (and sometimes pull-downs) enabled in software. Internal pull-ups are typically $20\ \text{k}\Omega$ – $50\ \text{k}\Omega$ , suitable for buttons but too high for I²C or high-speed lines.

Forbidden Band

Every logic family defines 4 voltage thresholds:

$V_{OL}$ : maximum voltage an output guarantees when driving LOW
$V_{OH}$ : minimum voltage an output guarantees when driving HIGH
$V_{IL}$ : maximum voltage an input will reliably interpret as LOW
$V_{IH}$ : minimum voltage an input will reliably interpret as HIGH

The region between $V_{IL}$ and $V_{IH}$ is the forbidden band. A signal in this range is neither a valid LOW nor a valid HIGH. The input’s output state is undefined. It may oscillate, latch at an intermediate voltage, or resolve differently on each device.

No signal should ever sit in the forbidden band in steady state. The noise margins ( $V_{IL} - V_{OL}$ for LOW, $V_{OH} - V_{IH}$ for HIGH) quantify how much voltage deviation the interface tolerates before entering the forbidden band.

The threshold voltage $V_{th}$ is the nominal switching point of a gate. It lies inside the forbidden band.

$V_{th}$ depends on the logic family:

CMOS: $V_{th} \approx V_{CC}/2$ . Scales with supply voltage. Symmetric noise margins.
TTL: $V_{th} \approx 1.4\ \text{V}$ . Fixed regardless of supply. Asymmetric noise margins (LOW margin is narrower).

$V_{th}$ is not a safe operating point. A signal held exactly at $V_{th}$ leaves the output in a high-gain linear region, consuming maximum current and producing maximum noise. The forbidden band exists because $V_{th}$ has manufacturing spread. No 2 gates switch at exactly the same voltage, and temperature shifts it further.

Signals pass through the forbidden band during transitions. A fast edge spends negligible time there. A slow edge, from a long cable, RC load, or weak driver, lingers in the band, causing the receiver to toggle unpredictably.

Schmitt Trigger Inputs

A standard digital input has a single switching threshold. A signal that crosses it slowly causes the output to toggle multiple times as noise kicks it back and forth across the threshold.

A Schmitt trigger input replaces the single $V_{th}$ with 2 thresholds:

$V_{T+}$ : upper threshold. Output switches HIGH when input rises above this.
$V_{T-}$ : lower threshold. Output switches LOW when input falls below this.

The hysteresis band is the voltage interval $[V_{T-},\ V_{T+}]$ . Its width is:

V_H = V_{T+} - V_{T-}

Switching behaviour is history-dependent:

If the output is currently LOW, it switches HIGH only when input exceeds $V_{T+}$ .
If the output is currently HIGH, it switches LOW only when input drops below $V_{T-}$ .
While the input is inside $[V_{T-},\ V_{T+}]$ , the output holds its last state regardless of input movement.

The transfer characteristic forms a loop rather than a single crossing point. The same input voltage can correspond to 2 different output states depending on which direction the signal arrived from. Noise smaller than $V_H$ cannot cause any transition regardless of where it occurs on the input.

A standard gate has 1 $V_{th}$ . Any noise that crosses it toggles the output. A Schmitt trigger requires the signal to travel the full width of the hysteresis band before the output changes.

Schmitt trigger inputs are tolerant of:

Slow-rising signals (RC-charged lines, long cables)
Noisy environments (motors, switching regulators near signal lines)
Mechanical switch bounce

Many MCU GPIO pins have a Schmitt trigger option that can be enabled per pin. UART RX, external interrupt pins, and I²C lines typically use Schmitt trigger inputs by default.

Push-Pull Outputs

A push-pull output has 2 transistors: a HIGH-side transistor connecting the pin to $V_{CC}$ , and a LOW-side transistor connecting it to GND. Exactly 1 is active at a time.

Driving HIGH: HIGH-side transistor conducts, LOW-side is off. Pin is actively connected to $V_{CC}$ .
Driving LOW: LOW-side transistor conducts, HIGH-side is off. Pin is actively connected to GND.

Output impedance is low in both states. Transitions are fast: the active transistor charges or discharges the line directly rather than through a resistor. No external pull resistor is required.

Push-pull cannot be used for shared buses. If 2 devices simultaneously drive conflicting levels, the HIGH-side transistor of one and the LOW-side of the other form a near-short circuit from $V_{CC}$ to GND, causing excessive current and potential damage.

Open-Collector Outputs

An open-collector output keeps only the LOW-side transistor. It can pull the line to GND (asserted) or release it entirely (Hi-Z). It cannot actively drive the line HIGH.

To produce a usable HIGH level, an external pull-up resistor connects the line to $V_{CC}$ . When no device asserts the line, the resistor pulls it HIGH passively.

Open-collector is used for:

Wired-AND bus
Multiple open-collector devices share 1 wire. Any device can pull the line LOW independently. The line is HIGH only when all devices release it. I²C uses this: any device can hold SDA or SCL LOW to stall the bus, enabling clock stretching and multi-master arbitration.
Voltage level shifting
The pull-up resistor connects to any supply voltage regardless of the MCU’s own logic level. A 3.3 V MCU can drive a 5 V bus by using a 5 V pull-up. The open-collector transistor only needs to pull to GND.
Short-circuit safety
If 2 devices simultaneously assert conflicting levels on a push-pull bus, a near-short circuit results. On an open-collector bus, 2 simultaneous LOW assertions are harmless. Both transistors pull to GND together.