Also known as data or delay flip-flop. Input is captured at rising edges of clock. Has 2 inputs: and and 1 output: . Built using 2 D latches.
To build a D flip-flop that’s triggered by falling edge of clock, the first NOT gate should be removed.
Characteristics
Characteristic Tabl
| D | Clk | Comment |
|---|---|---|
| 0 | ↑ | Reset |
| 1 | ↑ | Set |
| X | 0 | No change |
| X | 1 | No change |
Excitation Table
| Current State (Q) | Next State (Q+) | D |
|---|---|---|
| 0 | 0 | 0 |
| 0 | 1 | 1 |
| 1 | 0 | 0 |
| 1 | 1 | 1 |
