D Flip-flop

Aka. data or delay flip-flop. Input is captured at rising edges of clock. Has 2 inputs: $D$ and $Clk$ and 1 output: $Q$. Built using 2 D latches.

To build a D flip-flop that’s triggered by falling edge of clock, the first NOT gate should be removed.

Characteristics

Characteristic tabl

Excitation table