D Latch

Aka. data or delay latch. Has 2 inputs: $D$ and $En$. Has 1 output: $Q$. An extension of SR latch. Can be made with NAND or NOR gates.

When $En$ is LOW, $Q$ is the stored value. When $En$ is HIGH, $Q=D$. If NOR gates were used instead, a NOT gate will be added to the $En$ input, and NOT gate of D input will be switched.

Generally less common than D flip-flops in modern synchronous designs due to their level-sensitive behavior which can lead to timing issues.

Truth Table